Dr. Jozef Mitros

U.S. Patents:

• 5,394,101 Method for detecting mobile ions;
• 6,424,005 LDMOS power device with oversized dwell
• 6,548,874 Higher voltage transistors for sub micron CMOS processes
• 6,660,603 Higher voltage drain extended MOS transistors with self-aligned channel and drain extensions
• 6,730,569 Field effect transistor with improved isolation structures
• 6,734,491 EEPROM with reduced manufacturing complexity
• 6,747,308 Single poly EEPROM with reduced area
• 6,770,933 Single Poly EEPROM with improved coupling ratio
• 6,806,541 Field Effect Transistor with Improved Isolation Structures
• 6,803,282 Methods for fabricating low CHC degradation MOSFET transistors
• 6,873,021 MOS transistors having higher drain current without reduced breakdown voltage
• 6,897,113 Single poly EEPROM with improved coupling ratio
• 6,930,005 Low cost fabrication method for high voltage, high drain current MOS transistor
• 6,958,269 Memory Device with Reduced Cell Size
• 6,979,615 System and method for forming a semiconductor with an analog capacitor using fewer structure steps
• 7,019,356 Memory device with reduced cell area
• 7,045,418 Semiconductor device including a dielectric layer having a gettering material located therein and a method of manufacture therefor
• 7,045,425 Bird's beak-less or STI-less OTP EPROM
• 7,060,556 DE MOS transistors with multiple capacitors and methods of fabrication
• 7,166,903 DE MOS transistors with multiple capacitors and methods of fabrication
• 7,307,309 EEPROM with etched tunneling window
• 7,344,947 Methods of performance improvement of HVMOS devices
• 7,471,570 Embedded EEPROM Array Techniques for Higher Density
• 7,498,219 Methods for reducing capacitor dielectric absorption and voltage coefficient of a capacitor using phosphorus implant
• 7,919,368 Area-efficient electrically erasable programmable memory cell
• 8,125,830 B2. Area-efficient electrically erasable programmable memory cell
  

  Publications:

  
  
• High Voltage (up to 20V) Devices Implementation in 0.13 um BiCMOS Process Technology for System-On-Chip (SOC) Design - R. Pan, B. Todd, Pinghai Hao, R. Higgins, D. Robinson, V. Drobny, Weidong Tian, Jianglin Wang, J. Mitros, M. Huber, S. Pillai, S. Pendharkar Conference: International Symposium on Power Semiconductor Devices and Ics - ISPSD , 2006
• High-Voltage Drain Extended MOS transistors for 0.18um Logic Cmos Process - J.Mitros,CY Tsai, H.Shichijo, K.Kuntz, A. Morton, D.Goodpaster, D. Mosher, T.Efland, IEEE Trans. on ED, vol 48, no 8, August 2001 & ESSDERC-2000
• Thickness dependence of stress-induced leakage currents in silicon oxide - E. F. Runnion, S. M. Goldstone, R. S. Scott, D. J. Dumin, L. Lie, and J. C. Mitros, IEEE Trans. Electron Devices, vol. 44, p. 993, June 1997.
• 16-60 V rated LDMOS show advanced performance in a 0.72 ?m evolution BiCMOS power technology - Tsai, C.-Y.; Efland, T.; Pendharkar, S.; Mitros, J.; Tessmer, A.; Smith, J.; Erdeljac, J.; Hutter, L. International Electron Devices Meeting - IEDM , pp. 367-370, 1997
• A 0.7 /spl mu/m linear BiCMOS/DMOS technology for mixed-signal/power applications Smith, J.; Tessmer, A.; Springer, L.; Madhani, P.; Erdeljac, J.; Mitros, J.; Efland, T.; Chin-Yu Tsai; Pendharkar, S.; Hutter, L. Bipolar/BiCMOS Circuits and Technology Meeting, 1997. Proceedings of the , Page(s): 155 -157
• A performance comparison between new reduced surface drain "RSD" LDMOS and RESURF and conventional planar power devices rated at 20 V - Efland, T.; Tsai, C.-Y.; Erdeljac, J.; Mitros, J.; Hutter, L. Power Semiconductor Devices and IC's, 1997. ISPSD '97., 1997 IEEE International Symposium on , Page(s): 185 -188
• Optimized 25 V, 0.34 m/spl Omega//spl middot/cm/sup 2/ very-thin-RESURF (VTR), drain extended IGFETs in a compressed BiCMOS process - Chin-Yu Tsai; Arch, J.; Efland, T.; Erdeljac, J.; Hutter, L.; Mitros, J.; Yang, J.-Y.; Yuan, H.-T. Int. Electron Devices Meeting, 1996., International , Page(s): 469 -472
• Limitations on oxide thicknesses in flash EEPROM applications - Runnion, E.F.; Gladstone, S.M., IV; Scott, R.S.; Dumin, D.J.; Lie, L.; Mitros, J. - Reliability Physics Symposium, 1996. 34th Annual Proceedings., IEEE International , Page(s): 93 -99
• Empirical model of MOSFET breakdown voltages - Jozef C. Mitros EEE Transactions on Computer-Aided Design of Integrated Circuits and Systems , vol. 12, no. 4, pp. 511-515, 1993
• Thickness dependence of low-level leakages in thin oxides - Gladstone, S.M., IV; Scott, R.S.; Runnion, E.F.; Hughes, T.W.; Dumin, D.J.; Mitros, J.C.; Lie, L. Physical and Failure Analysis of Integrated Circuits, 1995., Proceedings of the 1995 5th International Symposium on the , Page(s): 121 -126
• Scaling Gate Electrode Thickness for 0.18 ?m CMOS Devices - P. Nunan, K. Cheung, M. Duane, J. Mitros, M. ter Beek Ndt & E International - NDT E INT, 1994
• Implant damage evaluation using SPIDER - Mitros, J.; Liu, J.; Chan, D. Integrated Reliability Workshop, 1994. Final Report., 1994 International , Page(s): 104 -105
• Single Gate EPROM Cell for the End-of-line Ionic Contamination Test - J. C. Mitros IEEE International Integrated Reliability Workshop Final Report - IRW , 1993
• Influence of ion sputtering and etching on the surface potential of passivated silicon - Danuta Brzesinska, Olga Ikanowicz, Jozef Mitros. Electron Technology 9, (3/4) 51 (1976), Microelectronics Reliability , vol. 16, no. 5, pp. 558-558, 1977
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